dorsaVi (ASX:DVL) locks in RRAM-CMOS chip design and the program finally moves to silicon

Tape-out clears the path to validation data, with compute-in-memory and TSMC-sourced wafers framing the commercial pitch

dorsaVi (ASX:DVL) has reached the moment its RRAM equity story has been pointing toward for the better part of two years. The company has finalised the full design package for its first integrated RRAM-CMOS validation chip, developed alongside NTU Singapore and ITRI Taiwan, and the program now moves from paper to fabrication.

For investors following the pivot from wearable sensors into ultra-edge hardware, this is the step that turns a roadmap into something testable. Up until today, the RRAM story has been a series of carefully sequenced de-risking announcements around temperature tolerance, exoskeleton performance projections and a robotics IP licence from NTU Singapore.

Today’s announcement is different. It commits the architecture to silicon. The chip locks in three specific capabilities. Self-checking write-and-verify circuitry for memory reliability, compute-in-memory macros that accumulate up to 64 inputs inside the array, and back-end-of-line integration that sits on top of commercial CMOS wafers sourced through TSMC.

The next 12 months stop being about projections and start being about whether the silicon does what the design says it will do.

We actually cover DVL in more depth here at PSR, which you can see in our research note here 

Why the TSMC wafer pathway is the quietly important part

The detail most investors will skim past is the choice to use commercial CMOS front-end wafers from TSMC, with partner-led back-end-of-line steps stacking the RRAM layer on top. In plain English, dorsaVi is not asking a foundry to build a bespoke transistor platform. It is using a standard one and adding the memory layer afterwards.

That matters because it lowers the cost and complexity of getting to silicon, and it keeps a future manufacturing pathway open without locking the company into a single fab partner. For a micro-cap pitching a non-volatile memory technology, manufacturability is half the credibility battle.

The skeptical read is that BEOL integration with partner-led steps still has to work at scale. The constructive read is that the program has been engineered around foundry compatibility from the start, which is the right discipline for a small company chasing high-value embedded markets.

Compute-in-memory is the feature that reframes the story

Write-and-verify circuitry is solid engineering. It improves reliability by reading back each programmed cell and re-tuning if the resistance state sits too close to the sensing threshold. But the feature that genuinely shifts how investors should think about this chip is the compute-in-memory mode.

The same RRAM array can either store digital data conventionally or use programmed resistance states as compute weights, accumulating across up to 64 inputs locally before producing a digital output. This is the architectural shift that lets a sensor stop streaming raw data to a processor and start producing decisions in place.

Tie that back to the exoskeleton thesis we covered earlier this year, where dorsaVi projected sensor count reductions of 25 to 50% and battery life more than doubling. Those numbers assume the sensor itself does the thinking. This validation chip is the silicon evidence that the architecture supports it.

What still has to happen before this becomes revenue

Design completion is not silicon performance. Tape-out comes next, then fabrication, then characterisation against the design targets. Each step can throw up surprises, particularly in the BEOL integration where dorsaVi depends on partner execution.

Our concern is the gap between a working validation chip and a product a defence prime, exoskeleton OEM or industrial AI customer designs into their roadmap. That gap is typically measured in years, not quarters, and it usually requires a 22-nanometre implementation behind the validation chip. Management has flagged that pathway explicitly, which is the right signal but also the right reminder that this is a multi-stage commercialisation.

The Investors Takeaway for dorsaVi

For two years dorsaVi has built the RRAM thesis through credible incremental milestones. The 150°C reliability data, the exoskeleton performance projections, the NTU robotics licence. Each one widened the addressable market without putting the architecture on the line. Today’s announcement changes that.

We think the investment debate from here narrows to two questions. Does the validation silicon hit the write-and-verify and compute-in-memory targets the design promises? And does dorsaVi convert those results into a credible 22-nanometre pathway with a named foundry partner? Both are answerable inside the next four quarters.

Our previous coverage of dorsaVi’s RRAM, exoskeleton and robotics pivot is available at stocksdownunder, and that context matters because today’s news only makes sense as the next chapter of a longer pivot from sensors into ultra-edge hardware.

Pitt Street Research Directors owns shares in the company discussed. This article reflects personal views and is not financial advice.