Nanoveu (ASX:NVU) Hits Tape Out Milestone as Chip Moves From Design to Manufacturing

Nanoveu Sends Chip Design to Foundry Tape Out

Nanoveu (ASX:NVU) reached an important chip manufacturing milestone today, known as the tape out phase.

For investors, especially those looking at opportunities in the semiconductor space, this is a key step because it marks the point where a chip design is effectively finalised and sent to the foundry for manufacturing.

In this note, we are going to break down what tape out actually means, why it matters for Nanoveu, and how it fits into the broader set of technical milestones the company still needs to execute.

We do cover NVU in our research, in which we recently valued the company at 19c a share, which you can read here.

Tape Out 101 The Design Is Done, Manufacturing Begins

The tape out phase is the point where a chip design is considered complete enough to be sent to the foundry, in this case TSMC, for manufacturing. In simple terms, it is the handover from design work to fabrication.

Tape out sits inside a longer validation journey that is often slow, difficult, and expensive. A typical flow runs from chip architecture and design, through verification and physical design, and then into tape out, which is one of the last major steps before wafers are actually produced. From there, the focus shifts to testing, validation, and eventually commercialisation.

So yes, this is a meaningful milestone for Nanoveu. But it is not the finish line. Management has been clear that there are still important stages ahead, including silicon validation and confirming real world performance characteristics.

From 22nm to 16nm Nanoveu Claims a Successful Node Scale Down

Stepping into what today’s 16nm ECS dot chip update actually tells investors, the key point is this. The design phase is now complete and the chip is moving into physical manufacturing.

Nanoveu has also made an important claim from an execution perspective. Management says the same underlying architecture used in the 22nm chip has successfully scaled down to 16nm, and has reached design sign off. In plain terms, they are saying the concept has not just worked in a larger node, but has translated into a smaller, more advanced manufacturing process.

So why does moving from 22nm to 16nm matter? Smaller nodes generally allow more transistors to fit into the same area. That typically translates into higher density, more memory capacity, and a more capable chip design overall. It can also enable higher integration, meaning fewer external components are needed around the chip, which can simplify the device design and potentially improve cost and reliability over time.

It is also worth noting the commercial context. The 22nm chip is already available and is being designed into customer platforms. That matters because it suggests the 16nm chip is not a brand new direction, but the next iteration of an existing product line that customers are already engaging with.

On the testing side, Nanoveu has said it has validated that software and workflow compatibility is maintained across generations. That is critical for adoption. Customers are far more likely to upgrade if the new chip fits into the same tooling, software stack, and development process, rather than forcing a complete redesign.

Power Gating and Dynamic Clocks The Architecture Built for Edge Devices

The company’s claim around energy efficiency comes back to what we would call the secret sauce, its fine grained power management.

Nanoveu describes a combination of fine grained power gating and dynamic clock control that is optimised for always on operation. In simple terms, the chip can shut down very small sections of itself when they are not needed, rather than keeping the whole system running. It can also scale clock speeds up or down depending on the workload, so it uses more power only when the task actually demands it.

If Nanoveu is truly targeting always on sensing and edge intelligence, this matters. Power efficiency is often the limiting factor for devices that need to stay active for long periods, especially in battery constrained or thermally constrained environments. A chip that can adapt its power draw in real time, without sacrificing responsiveness, can be a meaningful differentiator.

One way investors can think about it is that the chip is constantly “listening” to the workflow requirements and adjusting its energy use accordingly. It is not literally using sensors in the traditional sense, but the idea is the same. The chip is managing power dynamically based on what the system is asking it to do.

Next Milestones First Silicon, Yield, Then Commercial Proof

For investors, the next milestones are now very clear and they are the checkpoints that will determine whether this tape out turns into a real commercial outcome.

First is first silicon. Nanoveu needs to show that the chips coming back from the foundry match the expected functionality and performance. This is where real data matters, including power consumption, stability, and whether the chip behaves as designed across different operating conditions.

Second is manufacturing yield. It is one thing to produce working chips in a first run, but the bigger question is whether yields are high and consistent as production scales. If yields are unstable, costs rise quickly and timelines can slip, even if the underlying design is sound.

Once those technical hurdles are cleared, the focus shifts to commercial execution. Investors should watch for customer engagements that move beyond evaluation into committed partnerships, design wins, and clearer signals around order timing.

From there, revenue visibility should start to emerge. That usually shows up through contracted programs, repeat orders, and management being able to provide more concrete guidance around volumes, pricing, and expected rollout timing.

Pitt Street Research Directors owns shares in the company discussed. This article reflects personal views and is not financial advice.