Nanoveu (ASX:NVU) Hits Silicon Milestone,16nm Chip Ready for TSMC Tape-Out

Nanoveu’s 16nm Chip Enters the Final Stretch.

Nanoveu (ASX: NVU) has made solid technical progress with its subsidiary EMASS completing the core integrated circuit work for its next generation 16nm ECS Dot Edge design. EMASS has now finished front end design, synthesis, and physical design, placing the chip in the final stages ahead of tape out and fabrication at TSMC. To put this milestone into context for investors, semiconductor programs typically move through a long and complex development chain, starting with architecture and RTL (Register-Transfer Level) design. The latter describes what the chip is actually supposed to do.

This is followed by verification, synthesis, place and route and timing closure, before finally reaching tape out. This announcement effectively confirms that EMASS has cleared the major design execution hurdles and is now approaching the final sign-off gate before fabrication, so-called tape out, which is where the final design is sent to a foundry in the form of very large data files.

From our perspective, this is an important derisking step that shows tangible engineering execution, while still leaving investors mindful that tape out and manufacturing remain critical next stages where timelines, cost control and yield will ultimately determine commercial outcomes.

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Chip Checkpoint

Once this stage is complete, shareholders should focus on the final GDS sign off, followed by tape out and fabrication at TSMC as the next key milestones. The announcement also highlights a meaningful architectural upgrade, with the new 16nm chip design replacing the previous 22nm ECS Dot architecture. Notably, the 16nm version integrates a Bluetooth Low Energy subsystem directly onto the chip, removing the need for external wireless components and reducing board space, design complexity and overall bill of materials. This makes the entire solution cheaper and faster.

In addition, memory bandwidth has been expanded through increased on-chip SRAM, which EMASS links to supporting larger neural networks, higher throughput vision processing and multi sensor workloads. Put simply, the company is designing the chip for data-heavy applications where more processing requires more local memory. These upgrades are complemented by improved power management, using a more fine grained power control fabric to support a lower power operating profile.

Better gains, better chip

For Nanoveu, this new chip architecture is expected to deliver meaningful gains, with management pointing to around 50% area savings and roughly 25% improvement in energy efficiency versus the prior design. Once tape out is completed and first silicon is received, the narrative shifts from design intent to measured performance. At that point, execution matters. Management has indicated it will run a structured validation program and release measured power and performance data based on actual silicon behaviour, which will be a critical step in building technical credibility and investor confidence.

The Investor’s Takeaway for NVU

We have covered Nanoveu extensively in our research and continue to value the business at 19c per share based on a peer weighted valuation framework from our prior coverage. In our view, the market is finally beginning to give the company credit for the progress it has made, and there remains further upside potential as long as execution stays on track. That said, investors should remain disciplined around risk. The key watch points are any delays to tape out timelines, slippage in program milestones, or fabrication issues once the chip enters manufacturing, as setbacks at this stage could impact both sentiment and valuation in the near term.

But if everything goes according top plan, Nanoveu will be in a position to commercialise its chip in 2026.